Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12130551 | Pellicle frame with stress relief trenches | Kuo-Hao Lee, You-Cheng Jhang, Han-Zong Pan, Jui-Chun Weng, Sheng Lin +1 more | 2024-10-29 |
| 12074162 | Structure and formation method of semiconductor device with capacitors | Guo-Jyun Luo, Chen-Chien Chang, Shiuan-Jeng Lin, Han-Zong Pan | 2024-08-27 |
| 12062686 | Structure and formation method of semiconductor device with capacitors | Guo-Jyun Luo, Chen-Chien Chang, Shiuan-Jeng Lin, Han-Zong Pan | 2024-08-13 |
| 12062687 | Semiconductor device including a capacitor | Hong-Yang CHEN, Tian Sheng Lin, Yi-Cheng Chiu, Hung-Chou Lin, Yi-Min Chen +1 more | 2024-08-13 |
| 11923425 | Shielding structure for ultra-high voltage semiconductor devices | Yi-Cheng Chiu, Tian Sheng Lin, Hung-Chou Lin, Yi-Min Chen | 2024-03-05 |
| 11726401 | Pellicle frame with stress relief trenches | Kuo-Hao Lee, You-Cheng Jhang, Han-Zong Pan, Jui-Chun Weng, Sheng Lin +1 more | 2023-08-15 |
| 11728374 | Semiconductor device including a capacitor | Hong-Yang CHEN, Tian Sheng Lin, Yi-Cheng Chiu, Hung-Chou Lin, Yi-Min Chen +1 more | 2023-08-15 |
| 11688804 | Semiconductor device with ring-shaped doped region and manufacturing method thereof | Yi-Cheng Chiu, Tien Sheng Lin, Sheng-Fu Hsu, Chen-Yi Lee | 2023-06-27 |
| 11588028 | Shielding structure for ultra-high voltage semiconductor devices | Yi-Cheng Chiu, Tian Sheng Lin, Hung-Chou Lin, Yi-Min Chen | 2023-02-21 |
| 11415878 | Pellicle frame with stress relief trenches | Kuo-Hao Lee, You-Cheng Jhang, Han-Zong Pan, Jui-Chun Weng, Sheng Lin +1 more | 2022-08-16 |
| 11145709 | Semiconductor device including a capacitor | Hong-Yang CHEN, Tian Sheng Lin, Yi-Cheng Chiu, Hung-Chou Lin, Yi-Min Chen +1 more | 2021-10-12 |
| 10879236 | Bootstrap metal-oxide-semiconductor (MOS) device integrated with a high voltage MOS (HVMOS) device and a high voltage junction termination (HVJT) device | Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Kuo-Ming Wu, Shiuan-Jeng Lin +4 more | 2020-12-29 |
| 10866276 | Method and system for aligning probe card in semiconductor device testing | Kai-Di Chuang, Tien-Chung Lee, Kang-Tai Peng | 2020-12-15 |
| 10748986 | Structure and formation method of semiconductor device with capacitors | Guo-Jyun Luo, Shiuan-Jeng Lin, Chen-Chien Chang, Han-Zong Pan | 2020-08-18 |
| 10679987 | Bootstrap metal-oxide-semiconductor (MOS) device integrated with a high voltage MOS (HVMOS) device and a high voltage junction termination (HVJT) device | Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Kuo-Ming Wu, Shiuan-Jeng Lin +4 more | 2020-06-09 |
| 10509071 | Method and system for aligning probe card in semiconductor device testing | Kai-Di Chuang, Tien-Chung Lee, Kang-Tai Peng | 2019-12-17 |
| 9680009 | High voltage semiconductor device | Karthick Murukesan, Yi-Cheng Chiu, Hung-Chou Lin, Chih-Yuan Chan, Yi-Min Chen +3 more | 2017-06-13 |
| 9331081 | Semiconductor structure and manufacturing method thereof | Chun-Ming Lin, Yu-Shine Lin, Bor-Wen Lai, Tsung-Lin Lee | 2016-05-03 |
| 6773937 | Method of verifying a mask for a mask ROM | Lien-Che Ho, Ming-Yu Lin | 2004-08-10 |