Issued Patents All Time
Showing 251–263 of 263 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7768072 | Silicided metal gate for multi-threshold voltage configuration | Chih-Hao Wang, Wei-Jung Lin, Huan-Tsung Huang, Carlos H. Diaz | 2010-08-03 |
| 7649233 | High performance transistor with a highly stressed channel | Chih-Hao Wang, Ta-Wei Wang | 2010-01-19 |
| 7564108 | Nitrogen treatment to improve high-k gate dielectrics | Chih-Hao Wang, Ta-Wei Wang, Shang-Chih Chen | 2009-07-21 |
| 7465972 | High performance CMOS device design | Chih-Hao Wang, Shang-Chih Chen, Ta-Wei Wang, Pang-Yen Tsai | 2008-12-16 |
| 7355235 | Semiconductor device and method for high-k gate dielectrics | Chih-Hao Wang, Shang-Chih Chen | 2008-04-08 |
| 7332407 | Method and apparatus for a semiconductor device with a high-k gate dielectric | Chih-Hao Wang, Shang-Chih Chen | 2008-02-19 |
| 7323392 | High performance transistor with a highly stressed channel | Chih-Hao Wang, Ta-Wei Wang | 2008-01-29 |
| 7279756 | Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof | Chih-Hao Wang, Chenming Hu | 2007-10-09 |
| 7253481 | High performance MOS device with graded silicide | Chih-Hao Wang, Ta-Wei Wang | 2007-08-07 |
| 7229893 | Method and apparatus for a semiconductor device with a high-k gate dielectric | Chih-Hao Wang, Shang-Chih Chen | 2007-06-12 |
| 7196924 | Method of multi-level cell FeRAM | Sheng-Chih Lai, Hsueh-Yi Lee, Hsiang-Lan Lung | 2007-03-27 |
| 7106088 | Method of predicting high-k semiconductor device lifetime | Chih-Hao Wang, Min-hwa Chi | 2006-09-12 |
| 6552921 | Circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory | Shyue-Yi Lee, Ta-Hui Wang | 2003-04-22 |