Issued Patents All Time
Showing 26–50 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8701054 | Boosting transistor performance with non-rectangular channels | Victor Moroz, Munkang Choi | 2014-04-15 |
| 8694942 | Filler cells for design optimization in a place-and-route system | Jyh Chwen Frank Lee, Dipankar Pramanik | 2014-04-08 |
| 8686512 | Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance | Victor Moroz, Dipankar Pramanik | 2014-04-01 |
| 8504969 | Filler cells for design optimization in a place-and-route system | Jyh Chwen Frank Lee, Dipankar Pramanik | 2013-08-06 |
| 8219961 | Method for compensation of process-induced performance variation in a MOSFET integrated circuit | Victor Moroz, Dipankar Pramanik, Kishore Singhal | 2012-07-10 |
| 8086990 | Method of correlating silicon stress to device instance parameters for circuit simulation | Victor Moroz, Dipankar Pramanik | 2011-12-27 |
| 8069430 | Stress-managed revision of integrated circuit layouts | Victor Moroz, Dipankar Pramanik | 2011-11-29 |
| 8035168 | Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance | Victor Moroz, Dipankar Pramanik | 2011-10-11 |
| 7949985 | Method for compensation of process-induced performance variation in a MOSFET integrated circuit | Victor Moroz, Dipankar Pramanik, Kishore Singhal | 2011-05-24 |
| 7926018 | Method and apparatus for generating a layout for a transistor | Victor Moroz, Mark Rubin | 2011-04-12 |
| 7908573 | Minimizing effects of interconnect variations in integrated circuit designs | — | 2011-03-15 |
| 7897479 | Managing integrated circuit stress using dummy diffusion regions | Dipankar Pramanik, Victor Moroz | 2011-03-01 |
| 7895548 | Filler cells for design optimization in a place-and-route system | Jyh Chwen Frank Lee, Dipankar Pramanik | 2011-02-22 |
| 7863146 | Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance | Victor Moroz, Dipankar Pramanik | 2011-01-04 |
| 7767515 | Managing integrated circuit stress using stress adjustment trenches | Victor Moroz, Dipankar Pramanik | 2010-08-03 |
| 7739095 | Method for determining best and worst cases for interconnects in timing analysis | Dipankar Pramanik | 2010-06-15 |
| 7681164 | Method and apparatus for placing an integrated circuit device within an integrated circuit layout | Victor Moroz | 2010-03-16 |
| 7669161 | Minimizing effects of interconnect variations in integrated circuit designs | — | 2010-02-23 |
| 7635618 | Integrated circuit devices with high and low voltage components and processes for manufacturing these devices | Gwo-Chung Tai | 2009-12-22 |
| 7600207 | Stress-managed revision of integrated circuit layouts | Victor Moroz, Dipankar Pramanik | 2009-10-06 |
| 7542891 | Method of correlating silicon stress to device instance parameters for circuit simulation | Victor Moroz, Dipankar Pramanik | 2009-06-02 |
| 7484198 | Managing integrated circuit stress using dummy diffusion regions | Dipankar Pramanik, Victor Moroz | 2009-01-27 |
| 6743679 | Integrated circuit devices with high and low voltage components and processes for manufacturing these devices | Gwo-Chung Tai | 2004-06-01 |
| 6703668 | Local interconnect formed using silicon spacer | Emmanuel de Muizon | 2004-03-09 |
| 6432770 | Semiconductor arrangement having capacitive structure and manufacture thereof | — | 2002-08-13 |