Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11652475 | Independent skew control of a multi-phase clock | Srirup Bagchi, Gaurav Bhojane | 2023-05-16 |
| 11223469 | System for serializing high speed data signals | Biman Chattopadhyay | 2022-01-11 |
| 11101830 | Calibration scheme for serialization in transmitter | Shourya Kansal, Biman Chattopadhyay | 2021-08-24 |
| 10659214 | Multi-level clock and data recovery circuit | Biman Chattopadhyay, Sanket Naik, Jayesh Wadekar | 2020-05-19 |
| 10608645 | Fast locking clock and data recovery circuit | Biman Chattopadhyay | 2020-03-31 |
| 10516523 | System for serializing high speed data signals | Biman Chattopadhyay | 2019-12-24 |
| 10491367 | Clock and data recovery (CDR) circuit | Biman Chattopadhyay | 2019-11-26 |
| 10236891 | Lock time measurement of clock and data recovery circuit | Manjunath Shet SN, Biman Chattopadhyay, Vishal Dilipbhai Nimbark | 2019-03-19 |
| 10236843 | High gain differential amplifier with common-mode feedback | Jayesh Wadekar, Biman Chattopadhyay | 2019-03-19 |
| 10205445 | Clock duty cycle correction circuit | Shourya Kansal, Biman Chattopadhyay, Jayesh Wadekar | 2019-02-12 |
| 10164798 | Driver circuit for transmitter | Biman Chattopadhyay | 2018-12-25 |
| 10142097 | System for serializing high speed data signals | Biman Chattopadhyay | 2018-11-27 |
| 9813069 | Half-rate bang-bang phase detector | Biman Chattopadhyay | 2017-11-07 |
| 9577848 | Decision feedback equalizer | Biman Chattopadhyay, Rajesh V. | 2017-02-21 |
| 9548855 | Method and apparatus for managing estimation and calibration of non-ideality of a phase interpolator (PI)-based clock and data recovery (CDR) circuit | Biman Chattopadhyay, Sujoy Chakravarty, Gopalkrishna Ullal Nayak | 2017-01-17 |
| 9509319 | Clock and data recovery circuit | Biman Chattopadhyay, Gopal Krishna Ullal Nayak, Sharath Bhat N | 2016-11-29 |