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Apparatus for managing clock duty cycle correction |
— |
2017-02-28 |
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Method and apparatus for managing estimation and calibration of non-ideality of a phase interpolator (PI)-based clock and data recovery (CDR) circuit |
Biman Chattopadhyay, Ravi Mehta, Gopalkrishna Ullal Nayak |
2017-01-17 |
| 9407424 |
Fast locking clock and data recovery using only two samples per period |
Bharathi Rahuldev Holla, Jagdish Chand Goyal, Biman Chattopadhyay, Sumantra Seth |
2016-08-02 |
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Architecture for VBUS pulsing in UDSM processes |
Sumantra Seth, Somasunder Kattepura Sreenath, Arakali Abhijith |
2015-06-23 |
| 8704550 |
Architecture for VBUS pulsing in UDSM processes |
Sumantra Seth, Somasunder Kattepura Sreenath, Abhijith Arakali |
2014-04-22 |
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Phase interpolator and a delay circuit for the phase interpolator |
Anant Shankar Kamath, Krishnaswamy Nagaraj, Sudheer K. Vemulapalli, Jayawardan Janardhanan, Karthik Subburaj +1 more |
2013-05-21 |
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Fast-locking delay locked loop |
Jayawardan Janardhanan, Samala Sreekiran |
2011-12-27 |
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Synchronous clock multiplexing and output-enable |
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2011-11-08 |
| 7683716 |
Constant output common mode voltage of a pre-amplifier circuit |
Ravi Jitendra Mehta, Sumantra Seth |
2010-03-23 |
| 6703872 |
High speed, high common mode range, low delay comparator input stage |
Pentakota A. Visvesvaraya |
2004-03-09 |