Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12175176 | Fast synthesis of logical circuit design with predictive timing | Peter Moceyunas, Jiong Luo, Casey The, Jovanka Ciric Vujkovic, Patrick Vuillod | 2024-12-24 |
| 11669665 | Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization | Vinicius Neves Possani, Eleonora Testa, Felipe dos Santos Marranghello, Christopher Casares, Jiong Luo +1 more | 2023-06-06 |
| 11120184 | Satisfiability sweeping for synthesis | Jiong Luo, Patrick Vuillod | 2021-09-14 |
| 11010511 | Scalable boolean methods in a modern synthesis flow | Eleonora Testa, Patrick Vuillod, Jiong Luo | 2021-05-18 |
| 10839117 | Robust exclusive sum-of-product (ESOP) refactoring | Patrick Vuillod, Jiong Luo, Winston J. Haaswijk | 2020-11-17 |
| 10740517 | Integrated circuit (IC) optimization using Boolean resynthesis | Patrick Vuillod, Jiong Luo | 2020-08-11 |
| 10394988 | Majority logic synthesis | Pierre-Emmanuel Gaillardon, Giovanni De Micheli | 2019-08-27 |
| 10380309 | Boolean logic optimization in majority-inverter graphs | Pierre-Emmanuel Gaillardon, Giovanni De Micheli | 2019-08-13 |
| 10325051 | Exact delay synthesis | Patrick Vuillod, Jiong Luo | 2019-06-18 |
| 10049174 | Exact delay synthesis | Patrick Vuillod, Jiong Luo | 2018-08-14 |
| 9685959 | Method for speeding up boolean satisfiability | Pierre-Emmanuel Gaillardon, Giovanni De Micheli | 2017-06-20 |
| 9130568 | Controllable polarity FET based arithmetic and differential logic | Pierre-Emmanuel Gaillardon, Giovanni De Micheli | 2015-09-08 |