Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11734489 | Circuit layout verification | Jinsik Yun, Mark Daniel Pogers, Jonathan C. White, Danny Chang, Lihhsing Ke | 2023-08-22 |
| 11341310 | Layout-versus-schematic (LVS) debugging and error diagnosis via type of graph matching | Wei-Shun Chuang, Chia-Wei Hsu | 2022-05-24 |
| 10970456 | Identifying root cause of layout versus schematic errors | Wei-Shun Chuang | 2021-04-06 |
| 10691867 | Identifying root cause of layout versus schematic errors | Wei-Shun Chuang | 2020-06-23 |
| 8826219 | Method and apparatus used for the physical validation of integrated circuits | — | 2014-09-02 |