Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Layout-versus-schematic (LVS) debugging and error diagnosis via type of graph matching

Layout-versus-schematic (LVS) debugging and error diagnosis via type of graph matching

US Patent 11341310 · Granted May 24, 2022

Estimated economic value: $47,952,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Semiconductor device and method of forming the same2025
Semiconductor device and method of manufacture2025
Multi-spectral scattering-matrix tomography2025
Method for forming semiconductor structure using fluorine to treat gate stack2025
Detection device preventing damage to detection module from heat generated by li2025
Semiconductor device and method2025
Low dropout regulator circuits, input/output device, and methods for operating a2025
Capacitor cell and structure thereof2024
Processor, operation method, and load-store device for implementation of accessi2024
Integrated circuit and method of manufacturing same2024
Semiconductor device and method of manufacturing same2024
Device and method for operating the same2024