Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11574675 | Temperature tracked dynamic keeper implementation to enable read operations | Vinay Kumar, Saurabh Porwal, Sudhir Kumar, Madhav Mansukh Padaliya | 2023-02-07 |
| 11302365 | Area efficient and high-performance wordline segmented architecture | Vinay Kumar, Neeraj Kapoor, Sudhir Kumar | 2022-04-12 |
| 9842642 | Two phase write scheme to improve low voltage write ability in dedicated read and write port SRAM memories | M. Sultan M. Siddiqui, Shailendra Sharad, Hemant Vats | 2017-12-12 |
| 9281030 | Controlling timing of negative charge injection to generate reliable negative bitline voltage | Prashant Dubey, Vaibhav Verma, Gaurav Ahuja, Sanjay Yadav | 2016-03-08 |
| 9001569 | Input trigger independent low leakage memory circuit | Sanjeev Kumar Jain, Vikas Gadi | 2015-04-07 |
| 8837229 | Circuit for generating negative bitline voltage | Prashant Dubey, Guarav Ahuja, Sanjay Yadav | 2014-09-16 |
| 8546251 | Compact read only memory cell | Vineet Kumar SACHAN, Deepak Sabharwal | 2013-10-01 |
| 8031541 | Low leakage ROM architecture | Vineet Kumar SACHAN, Deepak Sabharwal | 2011-10-04 |
| 8031542 | Low leakage ROM architecture | Vineet Kumar SACHAN, Deepak Sabharwal | 2011-10-04 |
| 7929347 | Compact virtual ground diffusion programmable ROM array architecture, system and method | Deepak Sabharwal | 2011-04-19 |
| 7609550 | Compact virtual ground diffusion programmable ROM array architecture, system and method | Deepak Sabharwal | 2009-10-27 |
| 7376013 | Compact virtual ground diffusion programmable ROM array architecture, system and method | Deepak Sabharwal | 2008-05-20 |
| 7301819 | ROM with a partitioned source line architecture | — | 2007-11-27 |
| 7035129 | Partitioned source line architecture for ROM | — | 2006-04-25 |