Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Low leakage ROM architecture

Low leakage ROM architecture

US Patent 8031542 · Granted Oct 4, 2011

Estimated economic value: $1,415,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Temperature tracked dynamic keeper implementation to enable read operations2023
Area efficient and high-performance wordline segmented architecture2022
Two phase write scheme to improve low voltage write ability in dedicated read an2017
Controlling timing of negative charge injection to generate reliable negative bi2016
Input trigger independent low leakage memory circuit2015
Circuit for generating negative bitline voltage2014
Compact read only memory cell2013
Compact read only memory cell2013
Compact read only memory cell2013
Low leakage ROM architecture2011
Low leakage ROM architecture2011
Low leakage ROM architecture2011