Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9318470 | Semiconductor device | Yoichi Matsumura, Wataru SATOU, Mitsumi Itou | 2016-04-19 |
| 8028264 | Semiconductor device and semiconductor device layout designing method | Junichi Shimada, Yoichi Matsumura, Takako Ohashi, Nobuyuki Iwauchi, Takeya Fujino +4 more | 2011-09-27 |
| 7913221 | Interconnect structure of semiconductor integrated circuit, and design method and device therefor | Hirofumi Miyashita, Chie Kabuo, Nobuyuki Iwauchi, Yoichi Matsumura, Tatsuo Gou +1 more | 2011-03-22 |
| 7269807 | Area ratio/occupancy ratio verification method and pattern generation method | Junichi Shimada, Mitsumi Ito, Kiyohito Mukai | 2007-09-11 |
| 6989597 | Semiconductor integrated circuit and method of manufacturing the same | Takeya Fujino | 2006-01-24 |
| 6818929 | Standard cell for plural power supplies and related technologies | Masanori Tsutsumi, Junichi Yano, Masayuki Matsuda | 2004-11-16 |
| 6708318 | Wiring resistance correcting method | Kazuhiro Satoh | 2004-03-16 |
| 6440780 | Method of layout for LSI | Takahiro Ichinomiya | 2002-08-27 |
| 5978572 | LSI wire length estimation and area estimation | Masahiko Toyonaga, Minako Fukumoto, Noriko Koshita | 1999-11-02 |