Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7237220 | High level synthesis method for semiconductor integrated circuit | Osamu Ogawa, Dai Hattori, Keiichi Kurokawa | 2007-06-26 |
| 7100136 | LSI design system | Miwaka Takahashi | 2006-08-29 |
| 6578182 | Delay analysis method and design assist apparatus of semiconductor circuit | Keiichi Kurokawa, Takuya Yasui | 2003-06-10 |
| 6532581 | Method for designing layout of semiconductor device, storage medium having stored thereon program for executing the layout designing method, and semiconductor device | Kazuo Tsuzuki | 2003-03-11 |
| 6499133 | Method of optimizing placement of elements | Keiichi Kurokawa | 2002-12-24 |
| 6496963 | Delay analysis method and design assist apparatus of semiconductor circuit | Keiichi Kurokawa, Takuya Yasui | 2002-12-17 |
| 6473890 | Clock circuit and method of designing the same | Takuya Yasui, Keiichi Kurokawa, Atsushi Takahashi, Yoji Kajitani | 2002-10-29 |
| 6415423 | LSI design system | Miwaka Takahashi | 2002-07-02 |
| 6367061 | Semiconductor integrated circuit and manufacturing method therefor, semiconductor macro cell and automatic layout method therefor, and mask processing method | Keiichi Kurokawa, Miwaka Takahashi, Minako Fukumoto, Noriko Koshita | 2002-04-02 |
| 6336205 | Method for designing semiconductor integrated circuit | Keiichi Kurokawa, Noriko Ishibashi | 2002-01-01 |
| 6263475 | Method for optimizing component placement in designing a semiconductor device by using a cost value | Toshiro Akino | 2001-07-17 |
| 6096092 | Automatic synthesizing method for logic circuits | Miwaka Takahashi, Yoshihiro Seko | 2000-08-01 |
| 6000829 | Semiconductor integrated circuit capable of compensating for flucuations in power supply voltage level and method of manufacturing the same | Keiichi Kurokawa, Miwaka Takahashi, Minako Fukumoto, Noriko Koshita | 1999-12-14 |
| 5999716 | LSI layout design method capable of satisfying timing requirements in a reduced design processing time | — | 1999-12-07 |
| 5978572 | LSI wire length estimation and area estimation | Fumihiro Kimura, Minako Fukumoto, Noriko Koshita | 1999-11-02 |
| 5963730 | Method for automating top-down design processing for the design of LSI functions and LSI mask layouts | Michiaki Muraoka, Hirokazu Iida | 1999-10-05 |
| 5896055 | Clock distribution circuit with clock branch circuits connected to outgoing and return lines and outputting synchronized clock signals by summing time integrals of clock signals on the outgoing and return lines | Hisato Yoshida, Michiaki Muraoka | 1999-04-20 |
| 5852562 | Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zones | Noriko Shinomiya, Masahiro Fukui, Toshiro Akino | 1998-12-22 |
| 5673200 | Logic synthesis method and logic synthesis apparatus | Michiaki Muraoka | 1997-09-30 |
| 5657243 | Method and apparatus for automatically arranging circuit elements in data-path circuit | Michiaki Muraoka | 1997-08-12 |
| 5490083 | Method and apparatus for classifying and evaluating logic circuit | Michiaki Muraoka, Toshiro Akino | 1996-02-06 |
| 5479657 | System and method for sorting count information by summing frequencies of usage and using the sums to determine write addresses | Toshiro Akino, Hiroaki Okude | 1995-12-26 |
| 5272645 | Channel routing method | Yoshiyuki Kawakami | 1993-12-21 |
| 5267177 | Method for VLSI layout pattern compaction by using direct access memory | Koichi Sato, Toshiro Akino | 1993-11-30 |
| 5187668 | Placement optimization system aided by CAD | Hiroaki Okude, Toshiro Akino | 1993-02-16 |