Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6292926 | Functional module model, pipelined circuit synthesis and pipelined circuit device | Masahiro Fukui, Masakazu Tanaka, Masaharu Imai, Yoshinori Takeuchi | 2001-09-18 |
| 6263475 | Method for optimizing component placement in designing a semiconductor device by using a cost value | Masahiko Toyonaga | 2001-07-17 |
| 5852562 | Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zones | Noriko Shinomiya, Masahiko Toyonaga, Masahiro Fukui | 1998-12-22 |
| 5757679 | Method and apparatus for modelling MOS transistor characteristics for semiconductor circuit characteristic analysis | Toshitsugu Sawai | 1998-05-26 |
| 5694052 | Method and system for analysis and evaluation of semiconductor circuit performance characteristic | Toshitsugu Sawai | 1997-12-02 |
| 5677249 | Semiconductor apparatus and production method for the same | Masahiro Fukui, Mizuki Segawa, Michikazu Matsumoto | 1997-10-14 |
| 5490083 | Method and apparatus for classifying and evaluating logic circuit | Masahiko Toyonaga, Michiaki Muraoka | 1996-02-06 |
| 5479657 | System and method for sorting count information by summing frequencies of usage and using the sums to determine write addresses | Masahiko Toyonaga, Hiroaki Okude | 1995-12-26 |
| 5468734 | Prophylactic and remedial preparation for diseases attendant on hyperglycemia, and wholesome food | Kenji Seri, Kazuko Sanai, Shigenori Negishi | 1995-11-21 |
| 5267177 | Method for VLSI layout pattern compaction by using direct access memory | Koichi Sato, Masahiko Toyonaga | 1993-11-30 |
| 5187668 | Placement optimization system aided by CAD | Hiroaki Okude, Masahiko Toyonaga | 1993-02-16 |
| 5159682 | System for optimizing a physical organization of elements of an integrated circuit chip through the convergence of a redundancy function | Masahiko Toyonaga, Hiroaki Okude | 1992-10-27 |