Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8024689 | Semiconductor integrated circuit apparatus with low wiring resistance | Noriko Shinomiya | 2011-09-20 |
| 7707523 | Method of fabricating a semiconductor device and a method of generating a mask pattern | Tadashi Tanimoto, Mitsumi Ito | 2010-04-27 |
| 7269807 | Area ratio/occupancy ratio verification method and pattern generation method | Junichi Shimada, Fumihiro Kimura, Mitsumi Ito | 2007-09-11 |
| 7174527 | Layout verification method and method for designing semiconductor integrated circuit device using the same | Masanori Itou | 2007-02-06 |
| 7171645 | Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device | Mitsumi Ito, Junichi Shimada, Hiroyuki Tsujikawa | 2007-01-30 |
| 7115478 | Method of fabricating a semiconductor device and a method of generating a mask pattern | Tadashi Tanimoto, Mitsumi Ito | 2006-10-03 |
| 7062732 | Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor device | Mitsumi Ito, Junichi Shimada, Hiroyuki Tsujikawa | 2006-06-13 |
| 6576147 | Method of layout compaction | — | 2003-06-10 |
| 6473882 | Method of layout compaction | — | 2002-10-29 |
| 6303251 | Mask pattern correction process, photomask and semiconductor integrated circuit device | Hidenori Shibata, Hiroyuki Tsujikawa | 2001-10-16 |
| 6183920 | Semiconductor device geometrical pattern correction process and geometrical pattern extraction process | Hiroyuki Tsujikawa, Hidenori Shibata | 2001-02-06 |