Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7911027 | Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device, and apparatus for generating pattern for semiconductor device | Mitsumi Itoh, Masatoshi Sawada, Junko Honma, Kenji Shimazaki, Hiroshi Benno | 2011-03-22 |
| 7307333 | Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor device | Mitsumi Itoh, Masatoshi Sawada, Junko Honma, Kenji Shimazaki, Hiroshi Benno | 2007-12-11 |
| 7278124 | Design method for semiconductor integrated circuit suppressing power supply noise | Kenji Shimazaki, Kazuhiro Sato, Takahiro Ichinomiya, Shozo Hirano, Masao Takahashi +1 more | 2007-10-02 |
| 7171645 | Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device | Mitsumi Ito, Junichi Shimada, Kiyohito Mukai | 2007-01-30 |
| 7114144 | Mask pattern inspecting method, inspection apparatus, inspecting data used therein and inspecting data generating method | Shinya Tokunaga, Tadashi Tanimoto | 2006-09-26 |
| 7062732 | Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor device | Mitsumi Ito, Junichi Shimada, Kiyohito Mukai | 2006-06-13 |
| 7039572 | Method of analyzing electromagnetic interference | Hidetoshi Narahara, Seijirou Kojima, Kenji Shimazaki, Kasumi Hamaguchi | 2006-05-02 |
| 6959250 | Method of analyzing electromagnetic interference | Kenji Shimazaki, Seijirou Kojima, Shouzou Hirano | 2005-10-25 |
| 6943129 | Interconnection structure and method for designing the same | Chihiro Hyoto, Kiyoshi Mukai, Hidenori Shibata | 2005-09-13 |
| 6876210 | Method and apparatus for analyzing electromagnetic interference | Kenji Shimazaki, Shouzou Hirano, Tatsuo Ohhashi, Takashi Mizokawa | 2005-04-05 |
| 6810340 | Electromagnetic disturbance analysis method and apparatus and semiconductor device manufacturing method using the method | Kenji Shimazaki, Shouzou Hirano, Ritsuko Kurazono, Masanori Tsutsumi, Kaori Matsui +1 more | 2004-10-26 |
| 6782347 | Method for optimizing electromagnetic interference and method for analyzing the electromagnetic interference | Shouzou Hirano, Takashi Mizokawa, Tatsuo Ohhashi, Kenji Shimazaki | 2004-08-24 |
| 6754598 | Electromagnetic interference analysis method and apparatus | Kenji Shimazaki, Shouzou Hirano | 2004-06-22 |
| 6718528 | Latch-up verifying method and latch-up verifying apparatus capable of varying over-sized region | Shinichi Kimura | 2004-04-06 |
| 6710449 | Interconnection structure and method for designing the same | Chihiro Hyoto, Kiyoshi Mukai, Hidenori Shibata | 2004-03-23 |
| 6490709 | Latch-up verifying method and latch-up verifying apparatus capable of varying over-sized region | Shinichi Kimura | 2002-12-03 |
| 6434730 | Pattern forming method | Mitsumi Ito, Seijiro Kojima, Masatoshi Sawada | 2002-08-13 |
| 6303251 | Mask pattern correction process, photomask and semiconductor integrated circuit device | Kiyohito Mukai, Hidenori Shibata | 2001-10-16 |
| 6183920 | Semiconductor device geometrical pattern correction process and geometrical pattern extraction process | Hidenori Shibata, Kiyohito Mukai | 2001-02-06 |