Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
DJ

David V. James

Sony: 52 patents #425 of 25,231Top 2%
Apple: 26 patents #1,196 of 18,612Top 7%
Cypress Semiconductor: 13 patents #135 of 1,852Top 8%
NMNetlogic Microsystems: 5 patents #36 of 186Top 20%
HP: 5 patents #933 of 7,018Top 15%
AIAdvanced Memory International: 3 patents #2 of 16Top 15%
AIAlexa Internet: 1 patents #10 of 25Top 40%
Palo Alto, CA: #153 of 9,675 inventorsTop 2%
California: #3,101 of 386,348 inventorsTop 1%
Overall (All Time): #20,726 of 4,157,543Top 1%
84 Patents All Time

Issued Patents All Time

Showing 51–75 of 84 patents

Patent #TitleCo-InventorsDate
6442644 Memory system having synchronous-link DRAM (SLDRAM) devices and controller David Gustavson, Hans A. Wiggers, Peter B. Gillingham, Cormac Michael O'Connell, Bruce Millar +9 more 2002-08-27
6421745 Asynchronous connections with scattering page tables for transmitting data from a producer device to a consumer device over an IEEE 1394 serial data bus Hisato Shima, Bruce Fairman 2002-07-16
6414971 System and method for delivering data packets in an electronic interconnect Glen D. Stone 2002-07-02
6389547 Method and apparatus to synchronize a bus bridge to a master clock Bruce Fairman, Glen D. Stone 2002-05-14
6374316 Method and system for circumscribing a topology to form ring structures Bruce Fairman, David Hunter 2002-04-16
6345352 Method and system for supporting multiprocessor TLB-purge instructions using directed write transactions Donald N. North 2002-02-05
6321304 System and method for deleting read-only head entries in multi-processor computer systems supporting cache coherence with mixed protocols 2001-11-20
6286067 Method and system for the simplification of leaf-limited bridges Jose-Luis Diaz, Hisato Shima, Glen D. Stone 2001-09-04
6249827 Method for transferring data associated with a read/write command between a processor and a reader circuit using a plurality of clock lines Bruce Millar, Cormac Michael O'Connell, Peter B. Gillingham, Brent Keeth 2001-06-19
6226723 Bifurcated data and command/address communication bus architecture for random access memories employing synchronous communication protocols David Gustavson, Hans A. Wiggers 2001-05-01
6208645 Time multiplexing of cyclic redundancy functions in point-to-point ringlet-based computer systems Glen D. Stone 2001-03-27
6133938 Descriptor mechanism for assuring indivisible execution of AV/C operations 2000-10-17
6108739 Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system Donald N. North, Glen D. Stone 2000-08-22
6035376 System and method for changing the states of directory-based caches and memories from read/write to read-only 2000-03-07
6006289 System for transferring data specified in a transaction request as a plurality of move transactions responsive to receipt of a target availability signal Glen D. Stone 1999-12-21
5961623 Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system Donald N. North, Glen D. Stone 1999-10-05
5898876 Efficient arbitration within point-to-point ringlet-based computer systems 1999-04-27
5895496 System for an method of efficiently controlling memory accesses in a multiprocessor computer system Glen D. Stone 1999-04-20
5860080 Multicasting system for selecting a group of memory devices for operation Glen D. Stone 1999-01-12
5845145 System for generating and sending a critical-world-first data response packet by creating response packet having data ordered in the order best matching the desired order Donald N. North, Glen D. Stone 1998-12-01
5841989 System and method for efficiently routing data packets in a computer interconnect Glen D. Stone 1998-11-24
5835742 System and method for executing indivisible memory operations in multiple processor computer systems with multiple busses Donald N. North, Glen D. Stone 1998-11-10
5829035 System and method for preventing stale data in multiple processor computer systems Glen D. Stone, Donald N. North 1998-10-27
5815695 Method and apparatus for using condition codes to nullify instructions based on results of previously-executed instructions on a computer processor Mario Nemirovsky 1998-09-29
5717952 DMA controller with mechanism for conditional action under control of status register, prespecified parameters, and condition field of channel command Kevin M. Christiansen, Bruce Eckstein 1998-02-10