Issued Patents All Time
Showing 26–50 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6879523 | Random access memory (RAM) method of operation and device for search engine systems | Jagadeesan Rajamanickam | 2005-04-12 |
| 6876558 | Method and apparatus for identifying content addressable memory device results for multiple requesting sources | Jagadeesan Rajamanickam | 2005-04-05 |
| 6847650 | System and method for utilizing a memory device to support isochronous processes | Glen D. Stone, Bruce Fairman | 2005-01-25 |
| 6845024 | Result compare circuit and method for content addressable memory (CAM) device | Sanjay M. Wanzakhade, Michael C. Stephens, Jr., Jagadeesan Rajamanickam | 2005-01-18 |
| 6810452 | Method and system for quarantine during bus topology configuration | Bruce Fairman, Richard K. Scheel | 2004-10-26 |
| 6778552 | Method and system for partitioning an extended network of 1394b devices into subclusters of fully capable and partially capable nodes | Jose-Luis Diaz, Glen D. Stone | 2004-08-17 |
| 6763426 | Cascadable content addressable memory (CAM) device and architecture | Jagadeesan Rajamanickam | 2004-07-13 |
| 6751697 | Method and system for a multi-phase net refresh on a bus bridge interconnect | Hisato Shima, Bruce Fairman, Scott Smyers, Glen D. Stone, Kazonubu Toguchi +1 more | 2004-06-15 |
| RE38514 | System for and method of efficiently controlling memory accesses in a multiprocessor computer system | Glen D. Stone | 2004-05-11 |
| 6728821 | Method and system for adjusting isochronous bandwidths on a bus | Bruce Fairman, David Hunter, Hisato Shima | 2004-04-27 |
| 6690309 | High speed transmission system with clock inclusive balanced coding | Hans Wiggors | 2004-02-10 |
| 6684315 | Method and system for supporting multiprocessor TLB-purge instructions using directed write transactions | Donald N. North | 2004-01-27 |
| 6647446 | Method and system for using a new bus identifier resulting from a bus topology change | Bruce Fairman, David Hunter, Hisato Shima | 2003-11-11 |
| 6633943 | Method and system for the simplification of leaf-limited bridges | Jose-Luis Diaz, Hisato Shima, Glen D. Stone | 2003-10-14 |
| 6631415 | Method and system for providing a communication connection using stream identifiers | Bruce Fairman, Hisato Shima | 2003-10-07 |
| 6584539 | Method and system for message broadcast flow control on a bus bridge interconnect | Bruce Fairman, Scott Smyers | 2003-06-24 |
| 6584550 | System and method for updating a head entry from read-only to read-write and allowing a list to expand in a cache-coherence sharing list | — | 2003-06-24 |
| 6567896 | System and method for deleting read-only head entries in multi-processor computer systems supporting cache coherence with mixed protocols | — | 2003-05-20 |
| 6557067 | System and method to effectively compensate for delays in an electronic interconnect | Scott Smyers, Glen D. Stone, Bruce Fairman | 2003-04-29 |
| 6539450 | Method and system for adjusting isochronous bandwidths on a bus | Bruce Fairman, David Hunter, Hisato Shima | 2003-03-25 |
| 6523108 | Method of and apparatus for extracting a string of bits from a binary bit string and depositing a string of bits onto a binary bit string | Jung-Jen Liu | 2003-02-18 |
| 6519657 | Method and device for identifying an active 1394A node attached to a 1394B network | Glen D. Stone, Scott Smyers, Jose-Luis Diaz | 2003-02-11 |
| 6502158 | Method and system for address spaces | Bruce Fairman | 2002-12-31 |
| 6496907 | System and method for updating from a read-only to a read-write entry and concurrently invalidating stale cache copies from head-to-tail and tail-to-head directions | — | 2002-12-17 |
| 6445711 | Method of and apparatus for implementing and sending an asynchronous control mechanism packet used to control bridge devices within a network of IEEE STD 1394 serial buses | Richard K. Scheel | 2002-09-03 |