Issued Patents All Time
Showing 151–175 of 184 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9887206 | Method of making split gate non-volatile memory cell with 3D FinFET structure | Chien-Sheng Su, Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Hieu Van Tran | 2018-02-06 |
| 9882033 | Method of manufacturing a non-volatile memory cell and array having a trapping charge layer in a trench | — | 2018-01-30 |
| 9793280 | Integration of split gate flash memory array and logic devices | Chun-Ming Chen, Jeng-Wei Yang, Chien-Sheng Su, Man-Tang Wu | 2017-10-17 |
| 9793279 | Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing | Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Mandana Tadayoni, Chien-Sheng Su | 2017-10-17 |
| 9721958 | Method of forming self-aligned split-gate memory cell array with metal gates and logic devices | Jeng-Wei Yang, Chun-Ming Chen, Man-Tang Wu, Feng Zhou, Xian Liu +1 more | 2017-08-01 |
| 9673208 | Method of forming memory array and logic devices | Jinho Kim, Chien-Sheng Su, Feng Zhou, Xian Liu, Prateep Tuntasood +1 more | 2017-06-06 |
| 9634020 | Method of making embedded memory device with silicon-on-insulator substrate | Chien-Sheng Su, Mandana Tadayoni | 2017-04-25 |
| 9633735 | System and method to inhibit erasing of portion of sector of split gate flash memory cells | Jinho Kim, Yuri Tkachev, Kai Man Yue, Xiaozhou Qian, Ning Bai | 2017-04-25 |
| 9634018 | Split gate non-volatile memory cell with 3D finFET structure, and method of making same | Chien-Sheng Su, Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Hieu Van Tran | 2017-04-25 |
| 9634019 | Non-volatile split gate memory cells with integrated high K metal gate, and method of making same | Feng Zhou, Xian Liu, Jeng-Wei Yang, Chien-Sheng Su | 2017-04-25 |
| 9601500 | Array of non-volatile memory cells with ROM cells | Jinho Kim, Vipin Tiwari, Xian Liu, Xiaozhou Qian, Ning Bai +1 more | 2017-03-21 |
| 9570581 | Method of forming a self-aligned stack gate structure for use in a non-volatile memory array | Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Stephan Wege, Nadia Miridi +7 more | 2017-02-14 |
| 9570592 | Method of forming split gate memory cells with 5 volt logic devices | Vipin Tiwari | 2017-02-14 |
| 9548380 | Non-volatile memory cell having a trapping charge layer in a trench and an array and a method of manufacturing therefor | — | 2017-01-17 |
| 9496369 | Method of forming split-gate memory cell array along with low and high voltage logic devices | Man-Tang Wu, Jeng-Wei Yang, Chien-Sheng Su, Chun-Ming Chen | 2016-11-15 |
| 9431407 | Method of making embedded memory device with silicon-on-insulator substrate | Chien-Sheng Su, Hieu Van Tran, Mandana Tadayoni, Jeng-Wei Yang | 2016-08-30 |
| 9330922 | Self-aligned stack gate structure for use in a non-volatile memory array and a method of forming such structure | Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Stephan Wege, Nadia Miridi +7 more | 2016-05-03 |
| 9306039 | Method of making split-gate memory cell with substrate stressor region | Mandana Tadayoni | 2016-04-05 |
| 9293204 | Non-volatile memory cell with self aligned floating and erase gates, and method of making same | Jinho Kim, Xian Liu | 2016-03-22 |
| 9293359 | Non-volatile memory cells with enhanced channel region effective width, and method of making same | Hieu Van Tran, Chien-Sheng Su, Prateep Tuntasood | 2016-03-22 |
| 9286982 | Flash memory system with EEPROM functionality | Hieu Van Tran, Hung Quoc Nguyen, Vipin Tiwari | 2016-03-15 |
| 9275748 | Low leakage, low threshold voltage, split-gate flash cell operation | Steven Lemke, Jinho Kim, Jong-Won Yoo, Alexander Kotov, Yuri Tkachev | 2016-03-01 |
| 9276005 | Non-volatile memory array with concurrently formed low and high voltage logic devices | Feng Zhou, Xian Liu | 2016-03-01 |
| 9245638 | Method of operating a split gate flash memory cell with coupling gate | Elizabeth Cuevas, Yuri Tkachev, Mandana Tadayoni, Henry A. Om'Mani | 2016-01-26 |
| 9018690 | Split-gate memory cell with substrate stressor region, and method of making same | Mandana Tadayoni | 2015-04-28 |