Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11764913 | Jitter self-test using timestamps | Raghunandan K. Ranganathan, Kannanthodath V. Jayakumar | 2023-09-19 |
| 11496234 | Synchronizing update of time of day counters using time stamp exchange over a control plane | — | 2022-11-08 |
| 11316522 | Correction for period error in a reference clock signal | Aslamali A. Rafi, Timothy A. Monk, William J. Anker | 2022-04-26 |
| 11245406 | Method for generation of independent clock signals from the same oscillator | Harihara Subramanian Ranganathan, Xue-Mei Gong, James D. Barnette, Nathan J. Shashoua | 2022-02-08 |
| 11228403 | Jitter self-test using timestamps | Raghunandan K. Ranganathan, Kannanthodath V. Jayakumar | 2022-01-18 |
| 11038521 | Spur and quantization noise cancellation for PLLS with non-linear phase detection | Aslamali A. Rafi, Russell Croman, James D. Barnette | 2021-06-15 |
| 10840897 | Noise canceling technique for a sine to square wave converter | Aslamali A. Rafi, Russell Croman | 2020-11-17 |
| 10404209 | Compensating for thermal lag in temperature compensated crystal oscillators | Joseph D. Cali, Rajesh Thirugnanam, Rahul Shukla | 2019-09-03 |
| 10164643 | Compensating for temperature-dependent hysteresis in a temperature compensated crystal oscillator | Joseph D. Cali, Rajesh Thirugnanam, Richard J. Juhn | 2018-12-25 |
| 9444406 | Amplifier topology achieving high DC gain and wide output voltage range | Michael H. Perrott, Timothy A. Monk | 2016-09-13 |
| 9207704 | Glitchless clock switching that handles stopped clocks | William J. Anker | 2015-12-08 |
| 8823414 | Multiple signal format output driver with configurable internal load | Rajesh Thirugnanam | 2014-09-02 |
| 8532243 | Digital hold in a phase-locked loop | Jerrell P. Hein, Kenneth Kin Yip Wong, Qicheng Yu | 2013-09-10 |
| 8242849 | Compensation for crystal offset in PLL-based crystal oscillators | William J. Anker | 2012-08-14 |
| 7459948 | Phase adjustment for a divider circuit | — | 2008-12-02 |
| 7443250 | Programmable phase-locked loop responsive to a selected bandwidth and a selected reference clock signal frequency to adjust circuit characteristics | Ronald B. Hulfachor, William J. Anker, Richard J. Juhn | 2008-10-28 |
| 7405628 | Technique for switching between input clocks in a phase-locked loop | Ronald B. Hulfachor, Shailesh Chitnis | 2008-07-29 |