Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Sifive › Krste Asanovic
KA

Krste Asanovic — 24 Patents

SISifive: 16 patents #2 of 55Top 4%
SGSilicon Graphics: 3 patents #151 of 758Top 20%
IIInternational Computer Science Institute: 1 patents #4 of 16Top 25%
MIT: 1 patents #4,386 of 9,367Top 50%
Oakland, CA: #218 of 4,380 inventorsTop 5%
California: #23,266 of 386,348 inventorsTop 7%
Overall (All Time): #168,038 of 4,157,543Top 5%
24 Patents All Time
Krste Asanovic has been granted 24 US patents while listed as an inventor at Sifive. The first was granted in 1998 and the most recent in December 2025. Krste Asanovic ranks #168,038 of 4,157,543 US inventors in our database (top 4.0%). Patent records list Krste Asanovic in Oakland, CA, US.

Issued Patents All Time

Showing 1–24 of 24 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12487829 Macro-op fusion for pipelined architectures Andrew Waterman, Josh Smith 2025-12-02
12468540 Technologies for prediction-based register renaming Andrew Waterman 2025-11-11
12437121 Efficient processing of masked memory accesses Andrew Waterman 2025-10-07
12430132 Technologies for interconnect address remapper with event recognition and register management David Parry, Drew Barbier, Josh Smith, Alexandre Solomatnikov 2025-09-30
12417103 Fusion with destructive instructions Andrew Waterman 2025-09-16
12346268 Address range encoding in system on a chip with securely partitioned memory space — 2025-07-01
12314191 Memory protection for vector operations Andrew Waterman 2025-05-27
12253959 Memory protection for gather-scatter operations Andrew Waterman 2025-03-18
12086067 Load-store pipeline selection for vectors Andrew Waterman 2024-09-10
11966290 Checker cores for fault tolerant processing Murali Vijayaraghavan 2024-04-23
11861365 Macro-op fusion Andrew Waterman 2024-01-02
11797308 Fetch stage handling of indirect jumps in a processor pipeline Joshua Aaron Smith, Andrew Waterman 2023-10-24
11687342 Way predictor and enable logic for instruction tightly-coupled memory and instruction cache Andrew Waterman 2023-06-27
11556413 Checker cores for fault tolerant processing Murali Vijayaraghavan 2023-01-17
11429392 Secure predictors for speculative execution Andrew Waterman 2022-08-30
11347507 Secure control flow prediction Alex Solomatnikov 2022-05-31
11301251 Fetch stage handling of indirect jumps in a processor pipeline Joshua Aaron Smith, Andrew Waterman 2022-04-12
11048515 Way predictor and enable logic for instruction tightly-coupled memory and instruction cache Andrew Waterman 2021-06-29
10996952 Macro-op fusion Andrew Waterman 2021-05-04
8321634 System and method for performing memory operations in a computing system Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson +1 more 2012-11-27 $4,571,000
7925839 System and method for performing memory operations in a computing system Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson +1 more 2011-04-12 $3,908,000
7398359 System and method for performing memory operations in a computing system Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson +1 more 2008-07-08 $1,303,000
7287140 System and technique for fine-grained computer memory protection Emmett Witchel 2007-10-23
5805875 Vector processing system with multi-operation, run-time configurable pipelines — 1998-09-08

Nearby-Ranked Inventors

Tracy Helen Fung24
Yang Li24
Bo Ching Jiang24
Shoham DEKEL24
David B. Coulter24
Akiko WATANO24
Walter Nistico24
Thomas W. Chalberg, Jr.24
Alan R. Dombrowski24