Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12261609 | Inter-PLL communication in a multi-PLL environment | Srinath Sridharan, Ankit Seedher, Purva Choudhary, Sandeep Sasi, Akash Gupta +5 more | 2025-03-25 |
| 12249996 | Counter design for a time-to-digital converter (TDC) | Manikanta Sakalabhaktula, Debasish Behera, Girisha Angadi Basavaraja, Nandakishore Palla, Chandrasekhar BG +1 more | 2025-03-11 |
| 12149255 | Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable | Ankit Seedher, Srinath Sridharan, Rakesh Gupta, Nitesh Naidu, Shivam Agrawal +2 more | 2024-11-19 |
| 12026028 | Preventing reverse-current flow when an integrated circuit operates using power supplies of different magnitudes | Rakesh Gupta, Shuvadeep Mitra, Anurag Pulincherry, Ankit Seedher | 2024-07-02 |
| 11967965 | Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable | Ankit Seedher, Srinath Sridharan, Rakesh Gupta, Nitesh Naidu, Shivam Agrawal +2 more | 2024-04-23 |
| 11923864 | Fast switching of output frequency of a phase locked loop (PLL) | Srinath Sridharan, Ankit Seedher, Purva Choudhary, Sandeep Sasi, Akash Gupta +1 more | 2024-03-05 |
| 11799487 | Fractional sampling-rate converter to generate output samples at a higher rate from input samples | Sandeep Sasi, Debasish Behera, Akash Gupta, Venkata Krishna Mohan Panchireddi | 2023-10-24 |
| 11736110 | Time-to-digital converter (TDC) to operate with input clock signals with jitter | Nandakishore Palla, Girisha Angadi Basavaraja, Debasish Behera, Manikanta Sakalabhaktula, Chandrashekar B G | 2023-08-22 |
| 11711087 | Reducing noise contribution in compensating for unequal successive time periods of a reference clock in a fractional-N phase locked loop | Sandeep Sasi, Harshavardhan Reddy | 2023-07-25 |
| 11658667 | Reduction of noise in output clock due to unequal successive time periods of a reference clock in a fractional-N phase locked loop | Sandeep Sasi, Harshavardhan Reddy | 2023-05-23 |
| 11592786 | Time-to-digital converter (TDC) measuring phase difference between periodic inputs | Debasish Behera, Girisha Angadi Basavaraja, Nandakishore Palla, Manikanta Sakalabhaktula, Chandrashekar BG +1 more | 2023-02-28 |
| 11588489 | Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lock | Rakesh Gupta, Nitesh Naidu, Srinath Sridharan, Ankit Seedher, Shivam Agrawal | 2023-02-21 |
| 10892765 | Relocking a phase locked loop upon cycle slips between input and feedback clocks | Ankit Seedher, Srinath Sridharan | 2021-01-12 |
| 10700669 | Avoiding very low duty cycles in a divided clock generated by a frequency divider | Nigesh Baladhandapani, Sharanaprasad Melkundi, Augusto Marques | 2020-06-30 |
| 10514720 | Hitless switching when generating an output clock derived from multiple redundant input clocks | Ankit Seedher, Augusto Marques, Srinath Sridharan, Kulbhushan Thakur | 2019-12-24 |
| 9742414 | Reducing errors due to non-linearities caused by a phase frequency detector of a phase locked loop | Augusto Marques, Srinath Sridharan, Ankit Seedher, Sriharsha Vasadi | 2017-08-22 |