Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12149255 | Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable | Raja Prabhu J, Ankit Seedher, Srinath Sridharan, Rakesh Gupta, Shivam Agrawal +2 more | 2024-11-19 |
| 11967965 | Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable | Raja Prabhu J, Ankit Seedher, Srinath Sridharan, Rakesh Gupta, Shivam Agrawal +2 more | 2024-04-23 |
| 11588489 | Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lock | Rakesh Gupta, Raja Prabhu J, Srinath Sridharan, Ankit Seedher, Shivam Agrawal | 2023-02-21 |