Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6187683 | Method for final passivation of integrated circuit | Giorgio De Santi, Luca Zanotti | 2001-02-13 |
| 6087729 | Low dielectric constant composite film for integrated circuits of an inorganic aerogel and an organic filler grafted to the inorganic material | Gianfranco Cerofolini, Giorgio De Santi | 2000-07-11 |
| 6067250 | Method and apparatus for localizing point defects causing leakage currents in a non-volatile memory device | Leonardo Ravazzi | 2000-05-23 |
| 5977586 | Non-volatile integrated low-doped drain device with partially overlapping gate regions | Cesare Clementi | 1999-11-02 |
| 5798279 | Method of fabricating non-volatile memories with overlapping layers | Cesare Clementi | 1998-08-25 |
| 5723350 | Process for fabricating a contactless electrical erasable EPROM memory device | Gabriella Fontana, Orio Bellezza | 1998-03-03 |
| 5717636 | EEPROM memory with contactless memory cells | Marco Dallabora, Giovanni Campardo | 1998-02-10 |
| 5707884 | Process for fabricating a contactless electrical erasable EPROM memory device | Gabriella Fontana, Orio Bellezza | 1998-01-13 |
| 5633822 | Method of programming a nonvolatile flash-EEPROM memory array using source line switching transistors | Giovanni Campardo, Marco Dallabora | 1997-05-27 |
| 5587946 | Method of reading, erasing and programming a nonvolatile flash-EEPROM memory arrray using source line switching transistors | Giovanni Campardo, Marco Dallabora | 1996-12-24 |
| 5568418 | Non-volatile memory in an integrated circuit | Cesare Clementi | 1996-10-22 |
| 5543633 | Process and structure for measuring the planarity degree of a dielectric layer in an integrated circuit and integrated circuit including means for performing said process | Aldo Losavio, Giorgio De Santi | 1996-08-06 |
| 5464784 | Method of fabricating integrated devices | Cesare Clementi | 1995-11-07 |
| 4987088 | Fabrication of CMOS devices with reduced gate length | Carlo Bergonzoni, Tiziana Cavioni | 1991-01-22 |
| 4808261 | Fabrication process for EPROM cells with oxide-nitride-oxide dielectric | Gabriella Ghidini | 1989-02-28 |
| 4719184 | Process for the fabrication of integrated structures including nonvolatile memory cells with layers of self-aligned silicon and associated transistors | Daniele Cantarelli, Pierangelo Pansana | 1988-01-12 |