Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7951712 | Interconnections having double capping layer and method for forming the same | Kyoung-Woo Lee, Soo-geun Lee, Ki-Chul Park | 2011-05-31 |
| 7605472 | Interconnections having double capping layer and method for forming the same | Kyoung-Woo Lee, Soo-geun Lee, Ki-Chul Park | 2009-10-20 |
| 7205666 | Interconnections having double capping layer and method for forming the same | Kyoung-Woo Lee, Soo-geun Lee, Ki-Chul Park | 2007-04-17 |
| 7037835 | Interconnections having double capping layer and method for forming the same | Kyoung-Woo Lee, Soo-geun Lee, Ki-Chul Park | 2006-05-02 |
| 6888261 | Alignment mark and exposure alignment system and method using the same | Seong-Il Kim, Sang-Il Han, Chang-Hoon Lee, Choung-Hee Kim | 2005-05-03 |
| 6881630 | Methods for fabricating field effect transistors having elevated source/drain regions | Jung-Woo Park, Gil-Gwang Lee, Tae-Hee Choe | 2005-04-19 |
| 6842028 | Apparatus for testing reliability of interconnection in integrated circuit | Jung Woo Kim, Chang-Sub Lee, Sam Young Kim, Young-Jin Wee, Ki-Chul Park | 2005-01-11 |
| 6740587 | Semiconductor device having a metal silicide layer and method for manufacturing the same | Jeong Hwan Yang, In-Sun Park, Byoung-Moon Yoon | 2004-05-25 |
| 6693446 | Apparatus for testing reliability of interconnection in integrated circuit | Jung Woo Kim, Chang-Sub Lee, Sam Young Kim, Young-Jin Wee, Ki-Chul Park | 2004-02-17 |
| 6690187 | Apparatus for testing reliability of interconnection in integrated circuit | Jung Woo Kim, Chang-Sub Lee, Sam Young Kim, Young-Jin Wee, Ki-Chul Park | 2004-02-10 |
| 6667253 | Alignment mark and exposure alignment system and method using the same | Seong-II Kim, Sang-II Han, Chang-Hoon Lee, Choung-Hee Kim | 2003-12-23 |
| 6645866 | Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step | Tai-Su Park, Kyung Won Park, Jung-Woo Park | 2003-11-11 |
| 6580134 | Field effect transistors having elevated source/drain regions | Jung-Woo Park, Gil-Gwang Lee, Tae-Hee Choe | 2003-06-17 |
| 6511888 | Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step | Tai-Su Park, Kyung Won Park, Jung-Woo Park | 2003-01-28 |
| 6451691 | Methods of manufacturing a metal pattern of a semiconductor device which include forming nitride layer at exposed sidewalls of Ti layer of the pattern | In-Sun Park, Kyung-Bum Koo, Young-Cheon Kim | 2002-09-17 |