Issued Patents All Time
Showing 76–89 of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7733689 | Methods of operating and designing memory circuits having single-ended memory cells with improved read stability | Rajiv V. Joshi, Vinod Ramadurai | 2010-06-08 |
| 7681628 | Dynamic control of back gate bias in a FinFET SRAM cell | Rajiv V. Joshi, Edward J. Nowak, Richard Q. Williams | 2010-03-23 |
| 7532501 | Semiconductor device including back-gated transistors and method of fabricating the device | Rajiv V. Joshi, Edward J. Nowak, Richard Q. Williams | 2009-05-12 |
| 7492628 | Computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell | Ching-Te Chuang, Jae-Joon Kim | 2009-02-17 |
| 7420836 | Single-ended memory cell with improved read stability and memory using the cell | Rajiv V. Joshi, Vinod Ramadurai | 2008-09-02 |
| 7417889 | Independent-gate controlled asymmetrical memory cell and memory using the cell | Ching-Te Chuang, Jae-Joon Kim | 2008-08-26 |
| 7400525 | Memory cell with independent-gate controlled access devices and memory using the cell | — | 2008-07-15 |
| 7382162 | High-density logic techniques with reduced-stack multi-gate field effect transistors | Meng-Hsueh Chiang, Ching-Te Chuang | 2008-06-03 |
| 7362606 | Asymmetrical memory cells and memories using the cells | Ching-Te Chuang, Jae-Joon Kim | 2008-04-22 |
| 7336105 | Dual gate transistor keeper dynamic logic | Ching-Te Chuang, Jente B. Kuang, Kevin John Nowka | 2008-02-26 |
| 7313012 | Back-gate controlled asymmetrical memory cell and memory using the cell | Ching-Te Chuang, Jae-Joon Kim | 2007-12-25 |
| 7298176 | Dual-gate dynamic logic circuit with pre-charge keeper | Hung C. Ngo, Ching-Te Chuang, Jente B. Kuang, Kevin John Nowka | 2007-11-20 |
| 7265589 | Independent gate control logic circuitry | Ching-Te Chuang, Jente B. Kuang, Kevin John Nowka | 2007-09-04 |
| 7177177 | Back-gate controlled read SRAM cell | Ching-Te Chuang, Jae-Joon Kim | 2007-02-13 |