Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7123049 | Output buffer circuit with control circuit for modifying supply voltage and transistor size | Takashi Satou, Peter Lee, Gouichi Yokomizo | 2006-10-17 |
| 7099183 | Semiconductor device | Masanao Yamaoka, Koichiro Ishibashi, Kenichi Osada | 2006-08-29 |
| 7003763 | Data processor | Ryo Sudo, Yasunori Matsumoto | 2006-02-21 |
| 7000140 | Data processor and data processing system | Haruyasu Okubo, Atsushi Kiuchi | 2006-02-14 |
| 6952112 | Output buffer circuit with control circuit for modifying supply voltage and transistor size | Takashi Satou, Peter Lee, Gouichi Yokomizo | 2005-10-04 |
| 6937059 | Output buffer circuit with control circuit for modifying supply voltage and transistor size | Takashi Satou, Peter Lee, Gouichi Yokomizo | 2005-08-30 |
| 6914803 | Low-power semiconductor memory device | Masanao Yamaoka, Koichiro Ishibashi, Kenichi Osada | 2005-07-05 |
| 6792493 | Data processing system having a card type interface with assigned addressing | Ikuya Kawasaki, Susumu Narita, Masato Nemoto | 2004-09-14 |
| 6657911 | Semiconductor device with low power consumption memory circuit | Masanao Yamaoka, Koichiro Ishibashi, Kenichi Osada | 2003-12-02 |
| 6594720 | Data processing system having a PC card type interface with assigned addressing | Ikuya Kawasaki, Susumu Narita, Masato Nemoto | 2003-07-15 |
| 6542982 | Data processer and data processing system | Yasuyuki Murakami, Kunihiko Nishiyama, Atsushi Kiuchi, Yuichi Takitsune | 2003-04-01 |
| 6434691 | Cell phones with instruction pre-fetch buffers allocated to low bit address ranges and having validating flags | Yasuyuki Murakami, Kunihiko Nishiyama, Atsushi Kiuchi, Yuichi Takitsune | 2002-08-13 |
| 6425039 | Accessing exception handlers without translating the address | Shinichi Yoshioka, Ikuya Kawasaki, Susumu Narita | 2002-07-23 |
| 6049844 | Microprocessor having a PC card type interface | Ikuya Kawasaki, Susumu Narita, Masato Nemoto | 2000-04-11 |
| 6038661 | Single-chip data processor handling synchronous and asynchronous exceptions by branching from a first exception handler to a second exception handler | Shinichi Yoshioka, Ikuya Kawasaki, Susumu Narita | 2000-03-14 |
| 5848247 | Microprocessor having PC card interface | Ikuya Kawasaki, Susumu Narita, Masato Nemoto | 1998-12-08 |
| 5774701 | Microprocessor operating at high and low clok frequencies | Mitsuyoshi Yamamoto, Shinichi Yoshioka, Susumu Narita, Ikuya Kawasaki, Susumu Kaneko +1 more | 1998-06-30 |
| 5564041 | Microprocessor for inserting a bus cycle in an instruction set to output an internal information for an emulation | Ikuya Kawasaki, Yoshiyuki Kondo, Kouji Hashimoto | 1996-10-08 |
| 5511178 | Cache control system equipped with a loop lock indicator for indicating the presence and/or absence of an instruction in a feedback loop section | Hiroshi Takeda | 1996-04-23 |
| 5278962 | System for logical address conversion data fetching from external storage and indication signal for indicating the information externally | Satoshi Masuda, Ikuya Kawasaki | 1994-01-11 |
| 4954942 | Software debugging system for writing a logical address conversion data into a trace memory of an emulator | Satoshi Masuda, Ikuya Kawasaki | 1990-09-04 |