Peter Lee has been granted 6 US patents while listed as an inventor at Renesas Technology . The first was granted in 1998 and the most recent in May 2010. Peter Lee ranks #779,687 of 4,157,543 US inventors in our database (top 18.8%). Patent records list Peter Lee in Kokubunji, JP.
Patents per Year Patents granted per year, 1998 to 2010 Bar chart with a peak of 2 patents in 2005. peak 2 1998: 1 patents 1998 2003: 1 patents 2003 2005: 2 patents 2005 2006: 1 patents 2006 2010: 1 patents 2010
Issued Patents All Time
Profile Widget
Showing 1–6 of 6 patents
Patent # Title Co-Inventors Date Approx Value ⓘ
7721234 Simulation method and simulation program Junji Sato , Goichi Yokomizo 2010-05-18
$76,000
7123049 Output buffer circuit with control circuit for modifying supply voltage and transistor size Takashi Satou , Shigezumi Matsui , Gouichi Yokomizo 2006-10-17
$111,000
6952112 Output buffer circuit with control circuit for modifying supply voltage and transistor size Takashi Satou , Shigezumi Matsui , Gouichi Yokomizo 2005-10-04
$185,000
6937059 Output buffer circuit with control circuit for modifying supply voltage and transistor size Takashi Satou , Shigezumi Matsui , Gouichi Yokomizo 2005-08-30
$67,000
6634015 Computer-readable storage media stored with a delay library for designing a semiconductor integrated circuit device Goichi Yokomizo 2003-10-14
$261,000
5742071 Wiringless logical operation circuits Shiroo Kamohara , Hitoshi Matsuo , Sigeo Ihara 1998-04-21
$228,000
