Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9940299 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li | 2018-04-10 |
| 9832009 | Collaborative clock and data recovery | Masum Hossain, Yikui Jen Dong, Arash Zargaran-Yazd | 2017-11-28 |
| 9569396 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li | 2017-02-14 |
| 9178647 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li | 2015-11-03 |
| 8855217 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li | 2014-10-07 |
| 8279948 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li | 2012-10-02 |
| 8130891 | Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data | Dennis Kim, Jason C. Wei, Yohan Frans, Todd Bystrom, Kevin S. Donnelly | 2012-03-06 |
| 7668271 | Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data | Dennis Kim, Jason C. Wei, Yohan Frans, Todd Bystrom, Kevin S. Donnelly | 2010-02-23 |
| 7308065 | Delay locked loop circuitry for clock delay adjustment | Kevin S. Donnelly, Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark G. Johnson +7 more | 2007-12-11 |
| 7248086 | Leakage compensation for capacitors in loop filters | Yohan Frans | 2007-07-24 |
| 7183805 | Method and apparatus for multi-mode driver | Yueyong Wang, Barry William Daly, Yohan Frans | 2007-02-27 |
| 7102390 | Method and apparatus for signal reception using ground termination and/or non-ground termination | Yohan Frans, Yueyong Wang | 2006-09-05 |
| 7084681 | PLL lock detection circuit using edge detection and a state machine | Michael Green, Yohan Frans, Dennis Kim, Todd Bystrom | 2006-08-01 |
| 7061273 | Method and apparatus for multi-mode driver | Yueyong Wang, Barry William Daly, Yohan Frans | 2006-06-13 |
| 7039147 | Delay locked loop circuitry for clock delay adjustment | Kevin S. Donnelly, Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark G. Johnson +7 more | 2006-05-02 |
| 6963232 | Compensator for leakage through loop filter capacitors in phase-locked loops | Yohan Frans | 2005-11-08 |
| 6879195 | PLL lock detection circuit using edge detection | Michael Green, Yohan Frans, Dennis Kim, Todd Bystrom | 2005-04-12 |
| 6856169 | Method and apparatus for signal reception using ground termination and/or non-ground termination | Yohan Frans, Yueyong Wang | 2005-02-15 |
| 6696829 | Self-resetting phase locked loop | Kun-Yung Chang | 2004-02-24 |
| 6539072 | Delay locked loop circuitry for clock delay adjustment | Kevin S. Donnelly, Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark G. Johnson +7 more | 2003-03-25 |
| 6014042 | Phase detector using switched capacitors | — | 2000-01-11 |
| 5532655 | Method and apparatus for AC/DC signal multiplexing | Kevin J. Negus | 1996-07-02 |
| 5379457 | Low noise active mixer | — | 1995-01-03 |