Issued Patents All Time
Showing 51–66 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5680361 | Method and apparatus for writing to memory components | Frederick A. Ware, John B. Dillon, Richard M. Barth, Billy Wayne Garrett, Jr., John Girdner Atwood, Jr. +1 more | 1997-10-21 |
| 5657481 | Memory device with a phase locked loop circuitry | Mark A. Horowitz | 1997-08-12 |
| 5638334 | Integrated circuit I/O using a high performance bus interface | Mark A. Horowitz | 1997-06-10 |
| 5606717 | Memory circuitry having bus interface for receiving information in packets and access time registers | Mark A. Horowitz | 1997-02-25 |
| 5537573 | Cache system and method for prefetching of data | Frederick A. Ware, Craig E. Hampel, Karnamadakala Krishnamohan | 1996-07-16 |
| 5513327 | Integrated circuit I/O using a high performance bus interface | Mark A. Horowitz | 1996-04-30 |
| 5511024 | Dynamic random access memory system | Frederick A. Ware, John B. Dillon, Richard M. Barth, Billy Wayne Garrett, Jr., John Girdner Atwood, Jr. | 1996-04-23 |
| 5499385 | Method for accessing and transmitting data to/from a memory in packets | Mark A. Horowitz | 1996-03-12 |
| 5473575 | Integrated circuit I/O using a high performance bus interface | Mark A. Horowitz | 1995-12-05 |
| 5446696 | Method and apparatus for implementing refresh in a synchronous DRAM system | Frederick A. Ware, James A. Gasbarro, John B. Dillon, Mark A. Horowitz, Matthew Murdy Griffin | 1995-08-29 |
| 5434817 | Dynamic random access memory system | Frederick A. Ware, John B. Dillon, Richard M. Barth, Billy Wayne Garrett, Jr., John Girdner Atwood, Jr. | 1995-07-18 |
| 5430676 | Dynamic random access memory system | Frederick A. Ware, John B. Dillon, Richard M. Barth, Billy Wayne Garrett, Jr., John Girdner Atwood, Jr. | 1995-07-04 |
| 5408129 | Integrated circuit I/O using a high performance bus interface | Mark A. Horowitz | 1995-04-18 |
| 5319755 | Integrated circuit I/O using high performance bus interface | Mark A. Horowitz | 1994-06-07 |
| 5243703 | Apparatus for synchronously generating clock signals in a data processing system | Mark A. Horowitz | 1993-09-07 |
| 5226133 | Two-level translation look-aside buffer using partial addresses for enhanced speed | George S. Taylor | 1993-07-06 |