Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6539535 | Programmable logic device having integrated probing structures | Ming Yang Wang, Swey-Yan Shei, Alon Kfir | 2003-03-25 |
| 6377912 | Emulation system with time-multiplexed interconnect | Stephen P. Sample, Mikhail Bershteyn, Jerry R. Bauer | 2002-04-23 |
| 6353552 | PLD with on-chip memory having a shadow register | Stephen P. Sample, Kevin A. Norman, Rakesh Patel, Chao-Chiang Chen | 2002-03-05 |
| 6317367 | FPGA with on-chip multiport memory | Stephen P. Sample, Kevin A. Norman, Rakesh Patel, Chao-Chiang Chen | 2001-11-13 |
| 6289494 | Optimized emulation and prototyping architecture | Stephen P. Sample | 2001-09-11 |
| 6285211 | I/O buffer circuit with pin multiplexing | Stephen P. Sample, Kevin A. Norman, Rakesh Patel | 2001-09-04 |
| 6259588 | Input/output buffer with overcurrent protection circuit | Stephen P. Sample, Kevin A. Norman, Rakesh Patel | 2001-07-10 |
| 6219284 | Programmable logic device with multi-port memory | Stephen P. Sample, Kevin A. Norman, Rakesh Patel, Chao-Chiang Chen | 2001-04-17 |
| 6184707 | Look-up table based logic element with complete permutability of the inputs to the secondary signals | Kevin A. Norman, Rakesh Patel, Stephen P. Sample | 2001-02-06 |
| 6151258 | Programmable logic device with multi-port memory | Stephen P. Sample, Kevin A. Norman, Rakesh Patel, Chao-Chiang Chen | 2000-11-21 |
| 6034857 | Input/output buffer with overcurrent protection circuit | Stephen P. Sample, Kevin A. Norman, Rakesh Patel | 2000-03-07 |
| 6020760 | I/O buffer circuit with pin multiplexing | Stephen P. Sample, Kevin A. Norman, Rakesh Patel | 2000-02-01 |
| 6011730 | Programmable logic device with multi-port memory | Stephen P. Sample, Kevin A. Norman, Rakesh Patel, Chao-Chiang Chen | 2000-01-04 |
| 6011744 | Programmable logic device with multi-port memory | Stephen P. Sample, Kevin A. Norman, Rakesh Patel, Chao-Chiang Chen | 2000-01-04 |
| 6002861 | Method for performing simulation using a hardware emulation system | Jon A. Batcheller | 1999-12-14 |
| 5960191 | Emulation system with time-multiplexed interconnect | Stephen P. Sample, Mikhail Bershteyn, Jerry R. Bauer | 1999-09-28 |
| 5870410 | Diagnostic interface system for programmable logic system development | Kevin A. Norman, Rakesh Patel, Stephen P. Sample | 1999-02-09 |
| 5821773 | Look-up table based logic element with complete permutability of the inputs to the secondary signals | Kevin A. Norman, Rakesh Patel, Stephen P. Sample | 1998-10-13 |
| 5812414 | Method for performing simulation using a hardware logic emulation system | Jon A. Batcheller | 1998-09-22 |
| 5796623 | Apparatus and method for performing computations with electrically reconfigurable logic devices | Jon A. Batcheller | 1998-08-18 |
| 5734581 | Method for implementing tri-state nets in a logic emulation system | Jon A. Batcheller | 1998-03-31 |
| 5661662 | Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation | Jon A. Batcheller | 1997-08-26 |
| 5657241 | Routing methods for use in a logic emulation system | Jon A. Batcheller | 1997-08-12 |
| 5612891 | Hardware logic emulation system with memory capability | Jon A. Batcheller | 1997-03-18 |
| 5452231 | Hierarchically connected reconfigurable logic assembly | Jon A. Batcheller | 1995-09-19 |