Issued Patents All Time
Showing 76–100 of 104 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7324394 | Single data line sensing scheme for TCCT-based memory cells | Jin-Man Han, Seong-Ook Jung | 2008-01-29 |
| 7277310 | Open digit line array architecture for a memory array | Charles L. Ingalls, David L. Pinney, Howard C. Kirsch | 2007-10-02 |
| 7254074 | Open digit line array architecture for a memory array | Charles L. Ingalls, David L. Pinney, Howard C. Kirsch | 2007-08-07 |
| 7193914 | Open digit line array architecture for a memory array | Charles L. Ingalls, David L. Pinney, Howard C. Kirsch | 2007-03-20 |
| 7006398 | Single data line sensing scheme for TCCT-based memory cells | Jin-Man Han, Seong-Ook Jung | 2006-02-28 |
| 6958931 | Bit line control and sense amplification for TCCT-based memory cells | Seong-Ook Jung | 2005-10-25 |
| 6903987 | Single data line sensing scheme for TCCT-based memory cells | Jin-Man Han, Seong-Ook Jung | 2005-06-07 |
| 6735113 | Circuit and method for implementing a write operation with TCCT-based memory cells | Seong-Ook Jung | 2004-05-11 |
| 6721220 | Bit line control and sense amplification for TCCT-based memory cells | Seong-Ook Jung | 2004-04-13 |
| 6529423 | Internal clock signal delay circuit and method for delaying internal clock signal in semiconductor device | Sang-Pyo Hong | 2003-03-04 |
| 6359459 | Integrated circuits including voltage-controllable power supply systems that can be used for low supply voltage margin testing and related methods | Sang-Pyo Hong | 2002-03-19 |
| 6222787 | Integrated circuit memory devices having improved sense and restore operation reliability | Il-Man Bae, Gi-Hong Kim | 2001-04-24 |
| 6184078 | Method for fabricating a capacitor for a dynamic random access memory cell | Yong-Cheol Bae | 2001-02-06 |
| 6100744 | Integrated circuit devices having improved internal voltage generators which reduce timing skew in buffer circuits therein | Seong-Min Wi | 2000-08-08 |
| 6087891 | Integrated power supply voltage generators having reduced susceptibility to parasitic latch-up during set-up mode operation | Yong-Cheol Bae | 2000-07-11 |
| 6079023 | Multi-bank memory devices having common standby voltage generator for powering a plurality of memory array banks in response to memory array bank enable signals | Yong-Cheol Bae | 2000-06-20 |
| 6055194 | Method and apparatus for controlling column select lines in a synchronous memory device | Dong-Il Seo | 2000-04-25 |
| 6046954 | Circuit for controlling internal voltage for output buffer of semiconductor memory device and method therefor | Yong-Cheol Bae | 2000-04-04 |
| 5953259 | Integrated circuit memory devices having cross-coupled isolation gate controllers which provide simultaneous reading and writing capability to multiple memory arrays | Gi-Hong Kim | 1999-09-14 |
| 5796293 | Voltage boosting circuits having backup voltage boosting capability | Yong-Cheol Bae | 1998-08-18 |
| 5781494 | Voltage pumping circuit for semiconductor memory device | Yong-Cheol Bae, Dong-Il Seo | 1998-07-14 |
| 5677877 | Integrated circuit chips with multiplexed input/output pads and methods of operating same | Tae-seong Jang | 1997-10-14 |
| 5677886 | Sense amplifier circuit in semiconductor memory device | Dong-Il Seo, Se-Jin Jeong | 1997-10-14 |
| 5608677 | Boosting voltage circuit used in active cycle of a semiconductor memory device | Chan-Jong Park, Byung-Chul Kim | 1997-03-04 |
| 5579276 | Internal voltage boosting circuit in a semiconductor memory device | Byung-Chul Kim | 1996-11-26 |