Bharat Kumar Rangarajan has been granted 13 US patents while listed as an inventor at Qualcomm . The first was granted in 2019 and the most recent in October 2024. Bharat Kumar Rangarajan ranks #362,438 of 4,157,543 US inventors in our database (top 8.7%). Patent records list Bharat Kumar Rangarajan in Bengaluru, IN.
Patents per Year Patents granted per year, 2019 to 2024 Bar chart with a peak of 3 patents in 2020. peak 3 2019: 2 patents 2019 2020: 3 patents 2020 2021: 1 patents 2021 2022: 3 patents 2022 2023: 2 patents 2023 2024: 2 patents 2024
Issued Patents All Time
Showing 1–13 of 13 patents
Patent # Title Co-Inventors Date Approx Value ⓘ
12130773
Quality of service (QoS) control of processor applications
Varun JINDAL
2024-10-29
$22,162,000
11880454
On-die voltage-frequency security monitor
Dipti Ranjan Pal , Keith Alan Bowman , Srinivas Turaga , Ateesh Deepankar De , Shih-Hsin Jason Hu +1 more
2024-01-23
$18,184,000
11630694
Core voltage regulator energy-aware task scheduling
Vijayakumar Dibbad , Prashanth Kumar KAKKIRENI , Srinivas Turaga
2023-04-18
$13,667,000
11604505
Processor security mode based memory operation management
Rajesh Arimilli , Rengarajan RAGAVAN
2023-03-14
$15,604,000
11507174
System physical address size aware cache memory
Srinivas Turaga
2022-11-22
$15,016,000
11493986
Method and system for improving rock bottom sleep current of processor memories
Rajesh Arimilli , Srinivas Turaga
2022-11-08
$15,064,000
11493980
Power controller communication latency mitigation
Vijayakumar Dibbad , Dipti Ranjan Pal , Keith Alan Bowman , Matthew Severson , Gordon P. Lee
2022-11-08
$15,064,000
11169593
Selective coupling of memory to voltage rails for different operating modes
Raghavendra Srinivas , Rajesh Arimilli
2021-11-09
$19,893,000
10831667
Asymmetric memory tag access and design
Chulmin Jung , Rakesh Misra
2020-11-10
$31,067,000
10691195
Selective coupling of memory to voltage rails based on operating mode of processor
Raghavendra Srinivas , Rajesh Arimilli
2020-06-23
$21,879,000
10664006
Method and apparatus for automatic switch to retention mode based on architectural clock gating
Rakesh Misra , Rajesh Arimilli
2020-05-26
$14,702,000
10466766
Grouping central processing unit memories based on dynamic clock and voltage scaling timing to improve dynamic/leakage power using array power multiplexers
Rajesh Arimilli , Rakesh Misra
2019-11-05
$20,667,000
10248558
Memory leakage power savings
Rakesh Misra
2019-04-02
$8,975,000