Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6892367 | Vertex based layout pattern (VEP): a method and apparatus for describing repetitive patterns in IC mask layout | Michal Palusinski, Mariusz Niewczas, Wojciech P. Maly, Andrezej Strojwas, Hans Eisenmann | 2005-05-10 |
| 6795574 | Method of correcting physically-conditioned errors in measurement of microscopic objects | Hans Hartmann, Hans Eisenmann, Hans-Juergen Brueck | 2004-09-21 |
| 6107207 | Procedure for generating information for producing a pattern defined by design information | Hans Hartmann | 2000-08-22 |