Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11263496 | Methods and systems to classify features in electronic designs | Abhishek Shendre | 2022-03-01 |
| 6892367 | Vertex based layout pattern (VEP): a method and apparatus for describing repetitive patterns in IC mask layout | Michal Palusinski, Wojciech P. Maly, Andrezej Strojwas, Thomas Waas, Hans Eisenmann | 2005-05-10 |