{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Safe", "item": "https://www.patentleaderboard.com/patent/D904724"}]}
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US Patent D904724 · Granted Dec 8, 2020

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