Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register

US Patent 9978116 · Granted May 22, 2018

Estimated economic value: $26,541,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Clock signal distribution using photonic fabric2025
Graphics processor with non-blocking concurrent architecture2025
Multistage collector for outputs in multiprocessor systems2025
Convolutional neural network on programmable two dimensional image processor2024
Convolutional neural network on programmable two dimensional image processor2024
Convolutional neural network on programmable two dimensional image processor2024
Convolutional neural network on programmable two dimensional image processor2024
Convolutional neural network on programmable two dimensional image processor2024
Convolutional neural network on programmable two dimensional image processor2024
Atomic memory update unit and methods2024
Synchronized data chaining using on-chip cache2023
Methods and apparatus for providing redundant networking capabilities for teleop2023