Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory node error correction

Memory node error correction

US Patent 9823986 · Granted Nov 21, 2017

Estimated economic value: $11,468,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method to track and clone data artifacts associated with distributed data proces2025
Neural network accelerator in DIMM form factor2025
Heterogeneous ML accelerator cluster with flexible system resource balance2025
Vector processing unit2025
Shared scratchpad memory with parallel load-store2025
Integrated circuit with a ring-shaped hot spot area and multidirectional cooling2025
Acceleration of model/weight programming in memristor crossbar arrays2025
Methods and heat distribution devices for thermal management of chip assemblies2025
Multiplier and adder in systolic array2025
Error checking for systolic array computation2025
Error checking for systolic array computation2025
Hardware-optimized neural architecture search2024