Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Dynamic adjustment of memory cell digit line capacitance

Dynamic adjustment of memory cell digit line capacitance

US Patent 9786348 · Granted Oct 10, 2017

Estimated economic value: $13,864,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory device control schemes, and associated methods, devices, and systems2025
Integrated assemblies having voltage sources coupled to shields and/or plate ele2025
Memory arrays with vertical transistors and the formation thereof2025
Sensing scheme for a memory with shared sense components2025
Word line driver circuitry including shared driver gates, and associated methods2025
Computer-readable media and methods for generating a geospatial image map2025
Storing memory array operational information in non-volatile subarrays2024
Storing memory array operational information in non-volatile subarrays2024
Storing memory array operational information in non-volatile subarrays2024
Integrated memory comprising secondary access devices between digit lines and pr2024
Integrated memory comprising secondary access devices between digit lines and pr2024
Single column select architecture for sense amplifier circuity2024