Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Deep silicon via as a drain sinker in integrated vertical DMOS transistor

Deep silicon via as a drain sinker in integrated vertical DMOS transistor

US Patent 9728632 · Granted Aug 8, 2017

Estimated economic value: $4,581,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Contaminant collection on SOI2025
Segmented Schottky diode2025
Segmented Schottky diode2024
Contaminant collection on SOI2024
Junction field effect transistor on silicon-on-insulator substrate2023
FET using trench isolation as the gate dielectric2022
SOI power LDMOS device2020
Method of forming high-voltage silicon-on-insulator device with diode connection2019
Structures to avoid floating resurf layer in high voltage lateral devices2019
Apparatus of a metal-oxide-semiconductor (MOS) transistor including a multi-spli2019
Low resistance sinker contact2018
SOI power LDMOS device2018