{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Internal spacers for nanowire transistors and method of fabrication thereof", "item": "https://www.patentleaderboard.com/patent/9508796"}]}
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Home › Internal spacers for nanowire transistors and method of fabrication thereof

Internal spacers for nanowire transistors and method of fabrication thereof

US Patent 9508796 · Granted Nov 29, 2016

Estimated economic value: $9,403,000 ⓘ

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