Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer

Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer

US Patent 9484459 · Granted Nov 1, 2016

Estimated economic value: $4,589,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Roller conveyor2025
Structures for a field-effect transistor that include a spacer structure2025
Conveyor device2025
Flushable pressure vessel2023
Self-sealing valve connection for pressure vessels2022
Transistor with phase transition material region between channel region and each2022
FDSOI channel control by implanted high-k buried oxide2020
Three-dimensional transistor with improved channel mobility2019
FDSOI channel control by implanted high-K buried oxide2018
Method of forming a semiconductor device structure using differing spacer widths2018
Epitaxial channel formation methods and structures2017
Method of forming a semiconductor device structure and such a semiconductor devi2016