Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for scalable liveness verification via abstraction refinement

Method for scalable liveness verification via abstraction refinement

US Patent 9483595 · Granted Nov 1, 2016

Estimated economic value: $3,150,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Equivalence checking of synthesized logic designs using generated synthesis hist2025
Equivalence checking of synthesized logic designs using generated synthesis hist2025
Co-debug of processing conditions of logic devices2025
Optimization of arithmetic expressions2024
Detection of unintended dependencies in hardware designs with pseudo-random numb2023
Scalable connectivity verification using conditional cut-points2021
Scalable connectivity verification using conditional cut-points2021
Scalable connectivity verification using conditional cut-points2021
Grouping and partitioning of properties for logic verification2020
Grouping and partitioning of properties for logic verification2020
Methods and systems for efficient identification of glitch failures in integrate2020
Initial-state and next-state value folding2020