Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System, method and apparatus for improving transactional memory (TM) throughput using TM region indicators

System, method and apparatus for improving transactional memory (TM) throughput using TM region indicators

US Patent 9411739 · Granted Aug 9, 2016

Estimated economic value: $12,367,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Sharing branch predictor resource for instruction cache and trace cache predicti2025
Next fetch predictor for trace cache2025
Program counter zero-cycle loads2025
Trace cache with filter for internal control transfer inclusion2025
Multi-degree branch predictor2025
Systems, methods, and apparatuses for heterogeneous computing2024
Systems, methods, and apparatuses for heterogeneous computing2023
Multi-table signature prefetch2023
Zero cycle load bypass in a decode group2022
Systems, methods, and apparatuses for heterogeneous computing2022
Indirect branch predictor based on register operands2022
History file for previous register mapping storage and last reference indication2021