Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Offset calibration for low power and high performance receiver

Offset calibration for low power and high performance receiver

US Patent 9385695 · Granted Jul 5, 2016

Estimated economic value: $7,179,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Time-to-digital converters (TDC) employing a single-stage delay pair and noise s2025
Phase interpolator (PI) with clamping circuit to limit operation to range having2025
Time to digital converter (TDC) circuit with self-adaptive time granularity and 2025
Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibra2025
Peak voltage amplitude detectors tolerant to process variation and device mismat2024
Calibrating a phase interpolator by amplifying timing differences2021
Multi-phase switching mode power supply with adaptive synchronous drivers2021
Low-power, low-latency time-to-digital-converter-based serial link2021
Receiver with cancellation of intrinsic offset from decision feedback equalizati2019
Offset nulling for high-speed sense amplifier2019
Apparatus and method for calibrating a receiver with a decision feedback equaliz2018
Systems and methods for chip to chip communication2017