Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and system for verifying the design of an integrated circuit having multiple tiers

Method and system for verifying the design of an integrated circuit having multiple tiers

US Patent 9330215 · Granted May 3, 2016

Estimated economic value: $3,857,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

SOIC chip architecture2025
Integrated circuit and method of manufacturing the same2025
Standard cell and semiconductor device including anchor nodes2025
Through-silicon via in integrated circuit packaging2025
Electronic device and manufacturing method thereof2024
Memory circuit and cache circuit configuration2024
Integrated circuit and method of manufacturing the same2023
Standard cell and semiconductor device including anchor nodes and method of maki2023
Electromagnetic shielding metal-insulator-metal capacitor structure2023
Memory circuit and cache circuit configuration2023
Multi-patterning graph reduction and checking flow method2023
Through-silicon vias in integrated circuit packaging2023