Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Instruction cache having a multi-bit way prediction mask

Instruction cache having a multi-bit way prediction mask

US Patent 9304932 · Granted Apr 5, 2016

Estimated economic value: $8,019,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Sharing loop cache instances among multiple threads in processor devices2025
System and method of VLIW instruction processing using reduced-width VLIW proces2023
System and method of VLIW instruction processing using reduced-width VLIW proces2023
Techniques for instruction perturbation for improved device security2023
Dynamic load balancing of hardware threads in clustered processor cores using sh2021
Methods and apparatus for storage and translation of entropy encoded software em2020
System and method of VLIW instruction processing using reduced-width VLIW proces2020
System and method of VLIW instruction processing using reduced-width VLIW proces2020
System and method for online functional testing for error-correcting code functi2020
Instruction-based synchronization of operations including at least one SIMD scat2019
Executing an operating system on processors having different instruction set arc2019
Current in-rush mitigation for power-up of embedded memories2019