Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System for electrical testing and manufacturing of a 3-D chip stack and method

System for electrical testing and manufacturing of a 3-D chip stack and method

US Patent 9250289 · Granted Feb 2, 2016

Estimated economic value: $1,325,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Testing a single chip in a wafer probing system2025
Testing a single chip in a wafer probing system2023
Logic built-in self-test of an electronic circuit2023
Device for positioning a semiconductor die in a wafer prober2022
Device for positioning a semiconductor die in a wafer prober2022
Device for positioning a semiconductor die in a wafer prober2022
Integrated circuit with optical tunnel2022
Integrated circuit with optical tunnel2022
Stressing integrated circuits using a radiation source2021
Stressing integrated circuits using a radiation source2021
Probe card alignment2021
Functional testing of high-speed serial links2020