{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Techniques and configurations associated with a capductor assembly", "item": "https://www.patentleaderboard.com/patent/9230944"}]}

Home › Techniques and configurations associated with a capductor assembly

Techniques and configurations associated with a capductor assembly

US Patent 9230944 · Granted Jan 5, 2016

Estimated economic value: $11,513,000 ⓘ

Assignee

Intel

Inventors

William J. Lambert (60 patents)
Michael J. Hill (36 patents)
Kaladhar Radhakrishnan (54 patents)

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