Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › High linearity SOI wafer for low-distortion circuit applications

High linearity SOI wafer for low-distortion circuit applications

US Patent 9165819 · Granted Oct 20, 2015

Estimated economic value: $1,187,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integration of compound-semiconductor-based devices and silicon-based devices2025
Under-source body contact2025
Switches in bulk substrate2025
Bipolar transistor with stepped emitter2025
Semiconductor structure with semiconductor-on-insulator region and method2024
Integrated circuit structure with through-metal through-substrate interconnect a2024
Photodetector with buried airgap reflectors2024
Field-effect transistors with a crystalline body embedded in a trench isolation 2024
Lateral bipolar transistor structure with superlattice layer and method to form 2024
Semiconductor structure having a thermal shunt below a metallization layer and i2023
Lateral bipolar junction transistor including a stress layer and method2023
Field-effect transistors with a body pedestal2023