Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Single event upset enhanced architecture

Single event upset enhanced architecture

US Patent 9054684 · Granted Jun 9, 2015

Estimated economic value: $17,962,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Forming and/or configuring stacked dies2024
Power distribution for active-on-active die stack with reduced resistance2023
Power delivery network for active-on-active stacked integrated circuits2022
Power distribution for active-on-active die stack with reduced resistance2021
Forming and/or configuring stacked dies2021
Programmable termination circuits for programmable devices2021
Integrated circuits designed for multiple sets of criteria2021
Circuit for and method of transmitting a signal in an integrated circuit device2020
Placing and routing an interface portion and a main portion of a circuit design2019
Circuit for and method of preventing multi-bit upsets induced by single event tr2017
Emulating power gating for a circuit design using a programmable integrated circ2017
Interconnect circuits having low threshold voltage P-channel transistors for a p2017